Functional Hardware Verification
When developing chips it is essential that they get verified thoroughly because it is very hard or impossible to fix them once they have been manufactured. In this class, you will learn how to program verification environments that verify chip functionality efficiently, as well as understand and leverage automation such as constrained random test generation and improve code reuse leveraging a standardized methodology. Programming experience including object-oriented programming. Data & Control structure. This course is developed by Cadence Design Systems, a global leader in electronic design automation. Cadence® software, hardware, IP, and services help customers around the world to overcome a range of technical and economic hurdles. This course will teach you how to think like a verification engineer. It will show the software development aspects you need to know to ensure chips are working as expected. You will learn how to implement verification environments.